TECHNOLOGY : VLSI
DOMAIN : IEEE TRANSACTIONS ON CORE VLSI
S.No CODE
TITLE,YEAR
1 VLSI001
A NOVEL CARRY-LOOK AHEAD APPROACH TO AN UNIFIED BCD AND BINARY ADDER/SUBTRACTOR 2008
2 VLSI002
SPECULATIVE CARRY GENERATION WITH PREFIX ADDER USING VHDL / VERILOG
2008
3 VLSI003
HIGHER RADIX AND REDUNDANCY FACTOR FOR FLOATING POINT SRT DIVISION USING VHDL / VERILOG 2008
4 VLSI004
AREA-EFFICIENT ARITHMETIC EXPRESSION EVALUATION USING DEEPLY PIPELINED FLOATING POINT CORES USING VHDL 2008
5 VLSI005
IMPROVING ERROR TOLERANCE FOR MULTITHREADED
REGISTER FILES 2008
6 VLSI006
REGISTER FOR PHASE DIFFERENCE BASED LOGIC 2007
7 VLSI007
DESIGNING EFFICIENT ONLINE TESTABLE REVERSIBLE ADDER WITH NEW REVERSABLE GATE 2007
8 VLSI008
NOVEL BCD ADDERS AND THEIR REVERSIBLE LOGIC IMPLEMENTATION FOR IEEE 754R FORMAT 2006
9 VLSI009
HIGH SPEED RECURSION ARCHITECTURE FOR MAP- BASED TURBO DECODERS 2007
10 VLSI010
CONCURRENT ERROR DETECTION IN REED SOLOMON ENCODERS AND DECODERS
2007
TECHNOLOGY : VLSI
DOMAIN : : IEEE TRANSACTIONS ON LOW POWER AND FPGA
1 VLSI011
LOW POWER DESIGN OF PRECOMPUTATION-BASED CONTENT-ADDRESSABLE MEMORY USING VHDL / VERILOG 2008
2 VLSI012
L-CBF: A LOW-POWER, FAST COUNTING BLOOM FILTER ARCHITECTURE USING VHDL
2008
3 VLSI013
LOW-POWER LEADING-ZERO COUNTING AND ANTICIPATION LOGIC FOR HIGH-SPEED FLOATING POINT UNITS 2008
4 VLSI014
FPGA IMPLEMENTATION OF LOW POWER PARALLEL MULTIPLIER 2007
5 VLSI015
LOW POWER MULTIPLIER WITH SUPERIOUS POWER SUPRESSION TECHNIQUE
2007
6 VLSI016
SHIFT INVERT CODING FOR LOW POWER VLSI 2004
TECHNOLOGY : VLSI
DOMAIN :IEEE TRANSACTIONS ON IMAGE PROCESSING
1 VLSI017
LOW POWER HARDWARE ARCHITECTURE FOR VBSME USING PIXEL TRUNCATION USING VHDL 2008
2 VLSI018
A MODELING OF A DYNAMICALLY RECONFIGURABLE PROCESSOR USING VHDL
2008
3 VLSI019
A PROCESSOR IN MEMORY ARCHITECTURE FOR MULTIMEDIA COMPRESSION
2007
4 VLSI020
A VLSI PROGRESSIVE CODING FOR WAVELET BASED IMAGE COMPRESSION 2007
5 VLSI021
SHIFT REGISTER BASED DATA TRANSPOSITION FOR COST EFFECTIVE DISCRETE COSINE TRANSFORM 2007
TECHNOLOGY: VLSI
DOMAIN: SECURITY AND COMMUNICATIONS
1 VLSI022
FPGA IMPLEMENTATION(S) OF A SCALABLE ENCRYPTION ALGORITHM USING VHDL
2008
2 VLSI023
DESIGN AND IMPLEMENTATION OF AES USING VHDL 2008
3 VLSI024
COST-EFFICIENT SHA HARDWARE ACCELERATORS 2008
4 VLSI025
EFFECTIVE USES OF FPGAS FOR BRUTE-FORCE ATTACK ON RC4 CIPHERS 2008
5 VLSI026
DESIGN OF REVERSIBLE FINITE FIELD ARITHMETIC CIRCUITS WITH ERROR DETECTION 2008
6 VLSI027
A ROBUST UART ARCHITECTURE BASED ON RECURSIVE RUNNING SUM FILTER FOR BETTER NOISE PERFORMANCE 2007
7 VLSI028
COMPACT HARDWAE DESIGN OF WHIRLPOOL HASHING CORE 2006
8 VLSI029
DIGITAL DESIGN OF DS-CDMA TRANSMITTER USING VHDL AND FPGA 2006
9 VLSI030
REAL TIME ADAPTIVE SPEECH WATERMARKING SCHEME FOR MOBILE APPLICATIONS 2003
10 VLSI031
A LIGHTWEIGHT ENCRYPTION METHOD SUITABLE FOR COPYRIGHT PROTECTION
1998
TECHNOLOGY:VLSI
DOMAIN:NON IEEE /APPLICATION
1 VLSIN001
RTL DESIGN AND SIMULATION OF MICRO CONTROLLER IN HDL
2 VLSIN002
HDL IMPLEMENTATION OF ERROR DETECTION AND CORRECTION CIRCUIT
3 VLSIN003
DAQ SYSTEM
4 VLSIN004
DESIGN AND IMPLEMENTATION OF DIRECT DIGITAL SYNTHESIZERS FOR WIRELESS APPLICATIONS
5 VLSIN005
MULTI LEVEL SECURITY SYSTEM